Computer systems include at least one processor and at least one memory. The memory stores information such as program instructions, data, and an operating system. The program instructions can include a compiler for compiling application programs. The operating system controls the processor and the memory for system operations and for execution of the program instructions.
In the execution of program instructions, data speculation techniques have been used to allow a compiler to schedule a load instruction before one or more logically prior store instructions, i.e., a store instructions that precedes the load instruction in program order, when the compiler has information to suggest that the load and store instructions are unlikely to conflict, i.e., reference the same portion of memory. A load instruction that is scheduled before a logically prior store instruction is known as an advanced load. Because load operations may take a relatively large amount of time to perform by a processor, significant time may be saved by performing a load ahead of schedule.
A hardware structure such as an advanced load address table (ALAT) may be used to monitor advanced loads to ensure that the advanced load does not conflict, i.e., access the same portion of memory, as the store instruction. The compiler schedules a check operation subsequent to the store instruction to query the ALAT to determine whether or not a conflict exists. If a conflict does not exist, then execution continues. If a conflict does exist, then a correction mechanism is invoked to re-do the load associated with the advanced load and any other instructions that were speculatively computed based on the value loaded by the advanced load.
To monitor an advanced load operation, the ALAT stores the target register number and the memory location of the advanced load instruction to identify the advanced load operation. If a store is performed to the memory location of the advanced load instruction, then the ALAT entry that contains that memory location number is invalidated. Accordingly, when a checking instruction included as part of an advanced load operation is executed to verify whether a store conflicted with the advanced load, the checking instruction will not find a valid ALAT entry associated with the target register and will cause the correction mechanism to be invoked.
When a called procedure uses the same physical registers as a calling procedure, the register values are typically saved prior to executing the procedure and restored in response to returning from the procedure. Unfortunately, the state of the ALAT is not typically saved across procedures. As a result, a problem can occur with an advanced load that is scheduled prior to a logically prior procedure call where the called procedure uses the same physical registers as the calling procedure. The problem is that a checking instruction associated with an advanced load may fail to detect a conflict with the advanced load when the following two events occur. First, a store that is logically prior to the advanced load instruction conflicts with the advanced load instruction. The store may be in either the called procedure or the calling procedure. Second, the called procedure performs second advanced load to the same target register as the first advanced load.
In response to the first event, the ALAT entry associated with the first advanced load is invalidated, as it should be, because the store conflicts with the first advanced load. The second event, however, causes a second ALAT entry to be created. Because the second advanced load uses the same target register as the first advanced load, the second ALAT entry includes the same target register number that the first ALAT entry included prior to being invalidated. As a result, the checking instruction associated with the first advanced load may detect a valid ALAT entry, i.e., the second ALAT entry, associated with the target register, and incorrectly determine that the first advanced load was successful. This problem generally prevents an advanced load from being performed prior to a procedure call where the calling procedure and the called procedure use the same physical registers.
It would be desirable for computer systems to be able to execute an advanced load prior to a procedure call where the calling procedure and the called procedure use the same physical registers.